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DETAILED DESCRIPTION
Current Mode Control and Slope
Compensation
The SP6652 is designed to use low value
ceramic capacitors and low value inductors
to reduce the converter ’s volume and cost
in portable devices. Current mode PWM
control was, therefore, chosen for the ease
of compensation when using ceramic output
capacitors and better transient line rejec -
tion, which is important in battery powered
applications. Current mode control spreads
the two poles of the output power train filter
far apart so that the modulator gain crosses
over at -20dB/decade instead of the usual
-40dB/decade. The external compensation
network is, simply, a series RC circuit con -
nected between ground and the output of the
internal transconductance error amplifier.
It is well known that an unconditional insta -
bility exists for any fixed frequency current-
mode converter operating above 50% duty
cycle. A simple, constant-slope compensa -
tion is chosen to achieve stability under these
conditions. The most common high duty
cycle application is a Li-Ion battery powered
regulator with a 3.3V output (D ≥ 90%). Since
the current loop is critically damped when the
compensation slope (denoted MC V ) equals
the negative discharge slope (denoted M2 V ),
the amount of slope compensation chosen
is, therefore:
M2 = dI L /dT OFF =-V OUT /L = -3.3V/4.7μH =
-702mA/μs
M2 V = M2?R PMOS
MC V = -M2 V = 702mA/μs?0.2? = 140mV/μs,
for R PMOS = 0.20?
The inductor current is sensed as a voltage
across the PMOS charging switch and the
NMOS synchronous rectifier (see BLOCK
DIAGRAM). During inductor current charge,
V(PV IN )-V(LX) represents the charging cur -
rent ramp times the resistance of the PMOS
charging switch. To keep the effective current
slope compensation constant (remembering
current is being compensated, not voltage)
the voltage slope must be proportional to
R PMOS . To account for this, the slope com -
pensation voltage is internally generated
with a bias current that is also proportional
to R PMOS .
Over Current Protection
In steady state closed loop operation the
voltage at the COMP pin controls the duty
cycle. Due to the current mode control and the
slope compensation, this voltage will be:
V( COMP )? { I LPK ? R PMOS + MC V ?T ON + V BE (Q1) }
The COMP node will be clamped when its
voltage tries to exceed V( BLIM ) + V BE (Q1).
The V BE (Q1) term is cancelled by V BE (Q2)
at the output of the translator. The correct
value of clamp voltage is, therefore:
V( BLIM ) = I L ( MAX )? R PMOS + MCV ?T ON
The I L(MAX) term is generated with a bias
current that is proportional to R PMOS , to
keep the value of current limit approximately
constant over process and temperature
variations, while the MC V ?T ON is generated
by a peak-holding circuit that senses the
amplitude of the slope compensation ramp
at the end of T ON .
There is minimum on-time (T ON ) generated
even if the COMP node is at zeroV, since
the peak current comparator is reset at the
end of a charge cycle and is held low during
a blanking time after the start of the next
charge cycle. This is necessary to swamp
the transients in the inductor current ramp
around switching times. The minimum T ON
(100ns, nominally) is not sufficient for the
COMP node to keep control of the current
Oct10-07 RevJ
SP6652 1A, High Efficiency, Current Mode PWM Buck Regulator
5
? 2007 Sipex Corporation
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